Several trends exist presently in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and requiring less power. A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a small battery as its primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device, which has memory and logic functions, integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device which retains its contents while power is not continuously applied thereto is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (“EEPROM”) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory which utilizes a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as a capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for an FeRAM. The memory size and memory architecture affects the read and write access times of an FeRAM. Table 1 illustrates exemplary differences between different memory types.
TABLE 1FeRAMPropertySRAMFlashDRAM(Demo)Voltage>0.5 VRead >0.5 V>1 V3.3 VWrite (12 V) (±6 V)Special TransistorsNOYESYESNO(High Voltage)(Low Leakage)Write Time<10 ns100 ms<30 ns60 nsWrite Endurance>1015<105>1015>1013Read Time<10 ns<30 ns<30 ns/<2 ns60 ns(single/multi bit)Read Endurance>1015>1015>1015>1013Added Mask for embedded0˜6-8˜6-8˜3Cell Size (F˜metal pitch/2)˜80 F2˜8 F2˜8 F2˜18 F2ArchitectureNDRONDRODRODRONon volatileNOYESNOYESStorageIQQP
The non-volatility of an FeRAM is due to the bistable characteristic of the ferroelectric memory cell. An FeRAM cell may be selected by two concurrent X and Y voltage pulses, respectively, wherein X and Y correspond to a specific bit line and word line, respectively, identified by horizontal and vertical decoder circuitry. The FeRAM cells of the capacitor array which receive only one voltage pulse remain unselected while the cell that receives both an X and Y voltage signal flips to its opposite polarization state or remains unchanged, depending upon its initial polarization state, for example.
FIG. 1A is the characteristic curve plot 10 of a Ferroelectric capacitor. Plot 10 illustrates the charge “Q” (y-axis), and the voltage “V” (x-axis), including the characteristics placement relationship of a “0” state (15), and a “1” state (20) in a typical FeCap. The voltage “V” (x-axis) ranges from 0 volts (30) to VCC (40). The charge “Q” (y-axis) ranges as high as P+R+S (50). The “0” state requires a charge greater than or equal to −(R+P+S), while the “1” state requires a charge greater than or equal to P+R+S to produce a state change of the FeCap.
Also in FIG. 1A, the quantity P is the “polarization charge”, R is the “Remnant charge”, and S is the “Saturation charge”. These quantities identify most characteristics of the FeCap Characteristic curve segment 60 represents the charge path from a “0” state cell, thru VCC (40) as charge is applied to a FeCap, and then thru curve segment 70 to the stable “1” state as the voltage is relaxed to the FeCap. FIG. 1B is the schematic symbol 80 of the Ferroelectric capacitor of FIG. 1A, and the typical ½VCC polling voltage which is applied to the plate line.
Several types of ferroelectric memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. Further, the single capacitor memory cell is generally broken down into two types; the 1C cell (one capacitor, or capacitor only) and the 1T1C cell (one transistor and one capacitor). The 1C cell has the obvious advantage of requiring one less access/isolation transistor and the accompanying silicon area, but may require more plate lines to limit the capacitance of the lines which couple all the cells wired in common. Because of this capacitance limitation, the 1C cell is seldom used. Both of the single capacitor memory cell types require less silicon area than the dual capacitor type (thereby increasing the potential density of the memory array), but are less immune to noise and process variations. Additionally, the 1C and 1T1C cell requires a voltage reference for determining a stored memory state.
The dual capacitor memory cell (referred to as a 2T2C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2T2C memory cell is more stable than a 1T1C memory cell. As illustrated in prior art FIG. 2, a 1T1C FeRAM cell 100 includes one transistor 112 and one ferroelectric storage capacitor 114. A bottom electrode of the storage capacitor 114 is connected to a drain terminal 115 of the transistor 112. The 1T1C cell 100 is read from by applying a signal to the gate 116 of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor 114 to the source of the transistor (the bit line BL) 118. A pulse signal is then applied to the top electrode contact (the drive line or plate line PL) 120. The potential on the bitline 118 of the transistor 112 is, therefore, the capacitor charge divided by the bitline capacitance. Since the capacitor charge is dependent upon the bistable polarization state of the ferroelectric material, the bitline potential can have two distinct values. A sense amplifier (not shown) is connected to the bitline 118 and detects the voltage associated with a logic value of either 1 or 0 associated with the FeRAM polarization. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bitline that Is not being read. In this manner, the memory cell data is retrieved.
A characteristic of a ferroelectric memory is that a read operation is destructive in some applications. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite or restore (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. If the drive line voltage was small enough not to switch the ferroelectric then the read operation was not destructive. In general, a non-destructive read requires a much larger capacitor than a destructive read and, therefore, requires a larger cell size.
As illustrated, for example, in prior art FIG. 3, a 2T2C memory cell 130 in a memory array couples to a bit line (“bitline”) 132 and an inverse of the bit line (“bitline-bar”) 134 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The 2T2C ferroelectric memory cell comprises two transistors 136 and 138 and two ferroelectric capacitors 140 and 142, respectively. The first transistor 136 couples between the bitline 132 and a first capacitor 140, and the second transistor 138 couples between the bitline-bar 134 and the second capacitor 142. The first and second capacitors 140 and 142 have a common terminal or plate (the plate line PL) 144 to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 136 and 138 of the 2T2C ferroelectric memory cell 130 are enabled (e.g., via their respective word line 146) to couple the capacitors 140 and 142 to the complementary logic levels on the bitline 132 and the bitline-bar line 134 corresponding to a logic state to be stored in memory. The plate line common terminal 144 of the capacitors is pulsed during a write operation to polarize the 2T2C memory cell 130 to one of the two logic states.
In a read operation, the first and second transistors 136 and 138 of the 2T2C memory cell 130 are enabled via the word line 146 to couple the information stored on the first and second capacitors 140 and 142 to the bitline 132 and the bitline-bar line 134, respectively. A differential signal (not shown) is thus generated across the bitline 132 and the bitline-bar line 134 by the 2T2C memory cell 130. A sense amplifier (not shown) that provides a signal corresponding to the logic level stored in memory senses the differential signal.
FIG. 4 illustrates an array portion 200 of the 1T1C memory cell structure as described for FIG. 2. The array 200 has a plurality of element groupings which operate together in a modular fashion to read and write to memory cells. FIG. 4, for example, shows two element groupings, in which each grouping comprises a sense amplifier (210 or 215) to sense a memory cell associated with a pair of bitlines (B1220 and B1-bar 222, or B2224 and B2-bar 226), which is accessed by one of a plurality of word lines (W1-W4) and plate lines (PL-PL), with each word line accessing a 1T1C memory cell 240. One element grouping, for example, comprises a sense amplifier 210, coupled to a pair of bitlines B1220 and B1-bar 222 through a set of bitline isolation transistors 230 controlled by an isolation switch line 235, to permit isolation from the sense amplifier 210, and a memory cell 240. The 1T1C memory cell 240 is comprised of a pass gate transistor 242 and a ferroelectric capacitor 244, which is accessed by its respective word line 246 and plate line 248.
In the same way, FIG. 5 illustrates an array portion 300 of the 2T2C memory cell structure as described for FIG. 3. The array 300 has a plurality of element groupings which operate together in a modular fashion to read and write to memory cells. FIG. 5, for example, shows two element groupings, in which each grouping comprises a sense amplifier (310 or 315) to sense a memory cell associated with a pair of bitlines (B1320 and B1-bar 322, or B2324 and b2-bar 326), which is accessed by one of a plurality of word lines (W1-W4) and plate lines (PL1-PL4), with each word line accessing a 2T2C memory cell 340. One element grouping, for example, comprises a sense amplifier 310, coupled to a pair of bitlines B1320 and B1-bar 322 through a set of bitline isolation transistors 330 controlled by an isolation switch line 335, to permit isolation from the sense amplifier 310, and a memory cell 340.
The 2T2C memory cell 340 is comprised of a pair of 1T1C type cells, with one coupled to the B1 bitline 320, and the other coupled to the B1 bitline-bar 322. The 2T2C memory cell 340 thus comprises two pass gate transistors and two ferroelectric capacitors. One pass gate transistor 342 is operable to couple ferroelectric capacitor 344 to B1 bitline 320, when accessed by the W1 word line 346, and PL1 plate line 348, while another pass gate transistor 352 is operable to couple ferroelectric capacitor 354 to B1-bar (bitline-bar 322), when accessed by its respective W1 word line 346, and PL1 plate line 348.
Currently, most FeRAM memory arrays apply the 2T2C cell structure of FIG. 5, rather than the 1T1C cell structure of FIG. 4, in part, because of the higher density of sense amplifiers in the 1T1C cell by comparison to the cell area required, as well as difficulties involved with supplying an accurate reference voltage to the sense amplifier of the 1T1C cell. As FeRAM memory cells become smaller, it becomes increasingly difficult to fit the sense amplifier into the same layout size pitch occupied by the memory cells. This problem is especially true of the higher densities of the “open bitline architecture” of the 1T1C cell and is exaggerated further in the dense 1C cell array structure.
As shown by the sensing scheme response plots 400 of FIG. 6, the 2T2C cell sensing scheme 410 is generally easy to implement, as the sense amplifier compares a charge driven from a bitline/bitline-bar at a “1” state 412 with a charge driven from a bitline-bar/bitline at a “0” state 414. The opposite state conditions on the bitline inputs to the sense amplifier eliminate the need for an exacting reference voltage level.
The 2T2C sensing scheme plot 410, begins at a time t0 416, at a ½ VCC level, where the pass gate transistors (e.g., 342 and 346 of FIG. 5) couple their respective FeRAM capacitors (e.g., 344 and 348 of FIG. 5) to their respective bitlines (e.g., B1320 and B1-bar 322 of FIG. 5), to produce the bitline charging plots 412 (the “1” state bitline) and 414 (the “0” state bitline), between times to 416 and tSENSE 418. At time tSENSE 418, the charge voltage on the bitlines is affected by the sensing operation of the sense amplifier, and changes the voltages as shown, and as discussed previously. Also as discussed, the states on the memory cells which were read must be re-written into the array, because of this charge altering read operation. However, the 2T2C cell needs twice as much area as the 1T1C cell.
Also shown in the sensing scheme response plots 400 of FIG. 6, is the 1T1C cell sensing scheme plots 420 and 430. The read response to a “1” state sensing operation is illustrated by plot 420, while the read response to a “0” state sensing operation is illustrated by plot 430. The 1T1C cell sensing generally is not easy to implement, as the sense amplifier must compare the read sense charge voltage produced by a target memory cell on one bitline/bitline-bar 422 or 434, to a reference voltage generated on the other bitline-bar/bitline 424 or 432.
The 1T1C sensing scheme plot 420, begins at a time t0 416, at a ½ VCC level, where the pass gate transistor (e.g., 242 of FIG. 4) couples FeRAM capacitor (e.g., 244 of FIG. 4) to bitline (e.g., B1220 of FIG. 4), to produce the bitline charging plots 422 (if a “1” state is sensed on the bitline) and 434 (if a “0” state is sensed on the bitline), between times t0 416 and tSENSE 418. Prior to sensing at time tSENSE 418, a reference voltage must be present, as indicated by line segment 426.
Relative to the “1” state sensing 422 of the plot 420, the reference 426 produced on the bitline opposite the read sensing of the memory cell, must be more negatively offset 428 as shown. Relative to the “0” state sensing 434 of the plot 430, the reference 436 produced on the bitline opposite the read sensing of the memory cell, must be more positively offset 438 as shown. As with the 2T2C cell sensing scheme, at time tSENSE 418, the charge voltage on the bitlines is affected by the sensing operation of the sense amplifier, and changes the voltages as shown, and as discussed previously. Also as discussed, the states on the memory cells which were read must be re-written into the array, because of this charge altering read operation. However, the 2T2C cell needs twice as much area as the 1T1C cell.
Similarly, the prior art DRAM cell sensing schemes of FIG. 7 illustrates the same essential differences between the 2T2C and the 1T1C cell (or the 1C cell) sensing schemes. The sensing scheme response plots 500 of FIG. 7 demonstrate that the 2T2C cell sensing scheme 510 generally is easy to implement, as the sense amplifier compares a charge driven from a bitline/bitline-bar at a “1” state 512 with a charge driven from a bitline-bar/bitline at a “0” state 514. The opposite state conditions on the bitline inputs to the sense amplifier, eliminates the need for generating a reference voltage level, but the 2T2C DRAM cell sensing also requires double the area of the 1T1C cell sensing scheme.
In the 1T1C DRAM, between time t0 516 and tSENSE 518, the bitline (or bitline-bar) voltage increases or decreases depending on the cell state “1” or “0”, respectively. During this same time, reference voltage VREF of the bitline-bar (or the bitline) remains unchanged at the precharge level. Therefore, the sense amplifier connected to the bitline and bitline-bar can sense a “1” or “0” state by detecting the voltage difference between the two bitlines. In the case of the FeRAM, both the “1” and the “0” states will give the same direction voltage change, but with differing magnitudes. Therefore, the DRAM as well as the FeRAM memory cell demonstrate the same need for a reference voltage.
1C cell sensing generally works the same as the 1T1C cell sensing operation.
Another prior art sensing scheme uses FeRAM “reference cells” or “dummy cells”. The dummy cell includes 2 ferroelectric capacitors (FeCaps) that are fabricated generally identically to each other and to the array of memory cells. Dummy cells operates by charging one of the two FeCaps to a “1” state, and charging another to a “0” state, and allowing the two FeCaps to be coupled to a bitline and to charge share to create a reference voltage which is substantially half of that developed by a ferroelectric memory cell. Dummy cells are only needed for certain memory cells, such as the 1T1C memory cells, that are not self-referenced, as with the DRAM or the 2T2C FeRAM sensing scheme.
Thus, conventional 2T2C FeRAM sensing schemes use excessive area for the applications considered. By contrast, conventional 1T1C and 1C cell sensing schemes, may use only half the area of the 2T2C cell, but require a means for generating an accurate reference voltage, and a more complex means of sensing. 1C cells require less area than the 1T1C cell, but as FeRAM cells become smaller, these cell sensing schemes tend to produce a density of sense amplifiers which may be beyond leading edge processes or interconnection methods.
Accordingly, there is a need for a simple sensing scheme for an FeRAM array of memory cells, which permits the high density use of a 1T1C and 1C cell structure in a small low power solution.